Entry point Debugging contd....

After initializing PTE, we move to next stages:

/*
 * If ever we are running from Flash, then we surely want the cache
 * to be enabled also for our execution instance...  We map 2MB of it
 * so there is no map overlap problem for up to 1 MB compressed kernel.
 * If the execution is in RAM then we would only be duplicating the above.
 */

What we do here is to take a magic addr value 0xC1E, OR it with Higher 12 PC bits

to obtain 0x80000C1E in R1.

Also, with higher 12 PC bits, we do only #2 lsl and add it with PTE addr 0x80004000

to obtain address 0x80006000 in R0.

We now save the value of R1 in [R0].

(Actually, 0x80006000 already had same value!, redundant code if we are not running

from FLASH memory!).

Next add R1 = R1 + 0x100000 = 0x80100C1E

store this value in R0+4 = 0x80006004 (Again redundant for RAM code!).

Now, branch back to _armv7_mmu_cache_on

_armv7_mmu_cache_on:

Drain write buffer. Again test ID_MMFR0 stored in R11 with VMSA(0xF).

If not equal, flush I,D, TLBs.

Now load C1,C0 reg to R0, 

R0 = I-cache enable, RR cache replacement and write buffers are set.

R0 = MMU Enable bit set

[R0=0x00C5587F]  

Load R3 containing Page table Pointer to C2,C0

[R3= 0x800040000]

Load R1=0xFFFFFFFF = -1

Load this R1 value to domain access control reg. C3,C0

Fig: This is the view of MMU regs. Note that highlighted DACR value changed from DO

to Manager after R1 was set)

**** Finally load R0 value to C1,C0 to Caches, TLBs and MMU ****

Now, we suddenly switch to VM context, Lauterbach goes for a toss if not properly

configured to handle MMU page tables!!

Fig: This is the view of MMU regs. after MMU enabled. Compare with previous pic to

see what register values actually changed when MMU was enabled!) 

If properly configured, we continue debugging. Above pic shows what we see when we

had Lauterbach configured properly to handle MMU changes!

Read back MMU control reg value to R0

R0 = 0x00C5187F

This ensures everything was configured correctly!

Next, load R0 with #0 and push it to C7,C4 reg to configure ISB (?!!)

Finally retrieve back original return addr previously secured in R12 reg. 

We have now returned back to start function, after successfully executing cache_on

Next, allocate malloc space above stack, but 64K max. (Refer to mem. mapping fig.)

Malloc space ends @0x8016e668

/*
 * Check to see if we will overwrite ourselves.
 *   r4 = final kernel address
 *   r5 = start of this image
 *   r2 = end of malloc space (and therefore this image)
 * We basically want:
 *   r4 >= r2 -> OK
 *   r4 + image length <= r5 -> OK
 */

This is the  state before we proceed further. Check above reg. values to see the 

behavior.