Bare Metal: PuppyBeagle interrupt controller (INTC) init file [intc.c/intc.h]

#include "sprint.h"
#include "intc.h"

void intc_init (void)
{
intc_reg *pintc = (intc_reg *) INTC_REG_BASE;

pintc->INTCPS_SYSCONFIG = INTC_SWRESET;

//Wait for reset complete
while (!pintc->INTCPS_SYSCONFIG)
;

sprint ("Inside intc_init\n");
}

and its header file

#ifndef __INTC_H

#define __INTC_H

#define INTC_REG_BASE 0x48200010

#define INTC_SWRESET 0x2

typedef struct {

unsigned int INTCPS_SYSCONFIG;//10

unsigned int INTCPS_SYSSTATUS;//0x14

unsigned int RSVD0[10];//3c

unsigned int INTCPS_SIR_IRQ;//40

unsigned int INTCPS_SIR_FIQ;//44

unsigned int INTCPS_CONTROL;//48

unsigned int INTCPS_PROTECTION;//4c

unsigned int INTCPS_IDLE;//50

unsigned int RSVD1[3];//5c

unsigned int INTCPS_IRQ_PRIORITY;//60

unsigned int INTCPS_FIQ_PRIORITY;//64

unsigned int INTCPS_THRESHOLD;//68

unsigned int RSVD2[5];//7c

unsigned int INTCPS_INTR0;//80

unsigned int INTCPS_MIR0;//84

unsigned int INTCPS_MIR_CLEAR0;//88

unsigned int INTCPS_MIR_SET0;//8c

unsigned int INTCPS_ISR_SET0;//90

unsigned int INTCPS_ISR_CLEAR0;//94

unsigned int INTCPS_PENDING_IRQ0;//98

unsigned int INTCPS_PENDING_FIQ0;//9c

unsigned int INTCPS_INTR1;//a0

unsigned int INTCPS_MIR1;//a4

unsigned int INTCPS_MIR_CLEAR1;//a8

unsigned int INTCPS_MIR_SET1;//ac

unsigned int INTCPS_ISR_SET1;//b0

unsigned int INTCPS_ISR_CLEAR1;//b4

unsigned int INTCPS_PENDING_IRQ1;//b8

unsigned int INTCPS_PENDING_FIQ1;//bc

unsigned int INTCPS_INTR2;//c0

unsigned int INTCPS_MIR2;//c4

unsigned int INTCPS_MIR_CLEAR2;//c8

unsigned int INTCPS_MIR_SET2;//cc

unsigned int INTCPS_ISR_SET2;//d0

unsigned int INTCPS_ISR_CLEAR2;//d4

unsigned int INTCPS_PENDING_IRQ2;//d8

unsigned int INTCPS_PENDING_FIQ2;//dc

unsigned int RSVD3[8];//fc

unsigned int INTCPS_ILR0;//100

unsigned int INTCPS_ILR1;

unsigned int INTCPS_ILR2;

unsigned int INTCPS_ILR3;

unsigned int INTCPS_ILR4;

unsigned int INTCPS_ILR5;

unsigned int INTCPS_ILR6;

unsigned int INTCPS_ILR7;

unsigned int INTCPS_ILR8;

unsigned int INTCPS_ILR9;

unsigned int INTCPS_ILR10;

unsigned int INTCPS_ILR11;

unsigned int INTCPS_ILR12;

unsigned int INTCPS_ILR13;

unsigned int INTCPS_ILR14;

unsigned int INTCPS_ILR15;

unsigned int INTCPS_ILR16;

unsigned int INTCPS_ILR17;

unsigned int INTCPS_ILR18;

unsigned int INTCPS_ILR19;

unsigned int INTCPS_ILR20;

unsigned int INTCPS_ILR21;

unsigned int INTCPS_ILR22;

unsigned int INTCPS_ILR23;

unsigned int INTCPS_ILR24;

unsigned int INTCPS_ILR25;

unsigned int INTCPS_ILR26;

unsigned int INTCPS_ILR27;

unsigned int INTCPS_ILR28;

unsigned int INTCPS_ILR29;

unsigned int INTCPS_ILR30;

unsigned int INTCPS_ILR31;

unsigned int INTCPS_ILR32;

unsigned int INTCPS_ILR33;

unsigned int INTCPS_ILR34;

unsigned int INTCPS_ILR35;

unsigned int INTCPS_ILR36;

unsigned int INTCPS_ILR37;

unsigned int INTCPS_ILR38;

unsigned int INTCPS_ILR39;

unsigned int INTCPS_ILR40;

unsigned int INTCPS_ILR41;

unsigned int INTCPS_ILR42;

unsigned int INTCPS_ILR43;

unsigned int INTCPS_ILR44;

unsigned int INTCPS_ILR45;

unsigned int INTCPS_ILR46;

unsigned int INTCPS_ILR47;

unsigned int INTCPS_ILR48;

unsigned int INTCPS_ILR49;

unsigned int INTCPS_ILR50;

unsigned int INTCPS_ILR51;

unsigned int INTCPS_ILR52;

unsigned int INTCPS_ILR53;

unsigned int INTCPS_ILR54;

unsigned int INTCPS_ILR55;

unsigned int INTCPS_ILR56;

unsigned int INTCPS_ILR57;

unsigned int INTCPS_ILR58;

unsigned int INTCPS_ILR59;

unsigned int INTCPS_ILR60;

unsigned int INTCPS_ILR61;

unsigned int INTCPS_ILR62;

unsigned int INTCPS_ILR63;

unsigned int INTCPS_ILR64;

unsigned int INTCPS_ILR65;

unsigned int INTCPS_ILR66;

unsigned int INTCPS_ILR67;

unsigned int INTCPS_ILR68;

unsigned int INTCPS_ILR69;

unsigned int INTCPS_ILR70;

unsigned int INTCPS_ILR71;

unsigned int INTCPS_ILR72;

unsigned int INTCPS_ILR73;

unsigned int INTCPS_ILR74;

unsigned int INTCPS_ILR75;

unsigned int INTCPS_ILR76;

unsigned int INTCPS_ILR77;

unsigned int INTCPS_ILR78;

unsigned int INTCPS_ILR79;

unsigned int INTCPS_ILR80;

unsigned int INTCPS_ILR81;

unsigned int INTCPS_ILR82;

unsigned int INTCPS_ILR83;

unsigned int INTCPS_ILR84;

unsigned int INTCPS_ILR85;

unsigned int INTCPS_ILR86;

unsigned int INTCPS_ILR87;

unsigned int INTCPS_ILR88;

unsigned int INTCPS_ILR89;

unsigned int INTCPS_ILR90;

unsigned int INTCPS_ILR91;

unsigned int INTCPS_ILR92;

unsigned int INTCPS_ILR93;

unsigned int INTCPS_ILR94;

unsigned int INTCPS_ILR95;

} intc_reg;

#endif