A quick look into the armv-entry.s file indicated that it uses macros:
get_irqnr_preamble and get_irqnr_and_base
to obtain the correct irq number for the interrupt generated. In my case, these macros located under entry-macro.s was left empty, resulting in the irq number to be some random value of 0xC02C1FC0, which later when compared against NR_IRQS failed.
Also, after this comparision, function irq_exit() gets called which actually modifies the register R0 containing previous erroneous irq value with a new value #3.
Now, since the irq was not disabled, we get interrupted again, but this time, the new value #3 appears, which, results in a pass against NR_IRQS comparision and hence entered puppy_irq_mask(), though with a wrong irq value. As a result, its unable to mask the correct GPT irq (37), and hence the system ends up in an infinite loop!
Next step: Indentify how to define the macros
Also, need to fix some bug that is currently calculating a wrong register address within INTC when it attempts to mask the register. FIXIT!
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